Zero to ASIC Course

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Zero to ASIC Course

Matt Venn

38 episodes

8 months ago

Interviews and news from the world of Open Source Silicon, ASICs and Semiconductors

All content for Zero to ASIC Course is the property of Matt Venn and is served directly from their servers with no modification, redirects, or rehosting. The podcast is not affiliated with or endorsed by Podjoint in any way.

Interviews and news from the world of Open Source Silicon, ASICs and Semiconductors

Episodes (20/38)

Zero to ASIC Course

Rest in peace Z80, long live the open source Z80!

00:00 intro 
00:56 z80 
04:54 Submitted to TT07 
06:52 NMOS 
08:22 dynamic memory 
10:28 z80 was everything in one chip 
12:00 hand layout 
14:10 most widely used CPU in the 80s 
17:27 Tiny Tapeout compromise 
18:56 voltage compatibility 
19:58 Fits in 4 TT tiles 
21:09 comparison table 
22:47 What is Tiny Tapeout 
24:28 next steps 
26:29 bond pads 
28:09 multicore z80 
28:59 pricing 
29:30 why not use an FPGA?
30:30 what to use for 1.8v core? 
31:02 all the classics? 
31:53 important to preserve the old chips 
32:50 the plan 
35:19 how can you help?

1 year ago

37 minutes 38 seconds

Zero to ASIC Course

Analog Philosophy - interview with Nordic’s principal IC scientist Carsten Wulff

* Carsten’s background and interest in analog circuit design * Open-source silicon and its benefits vs. challenges * Analog design tools evolution * Obstacles that hinder wider adoption of open-source silicon tools * Advice on approaching an analog design journey

1 year ago

30 minutes 46 seconds

Zero to ASIC Course

Chips in days with Minimal Fab - An interview with Leo Moser

Talking about the minimal fab with Leo Moser. Leo recently won a competition run by minimal fab and had a design fabricated.

He's published a few blog posts about it here:

About the Minimal Fab: https://mole99.uber.space/2023/Minimal_Fab/About%20Minimal%20Fab%20and%20the%20ICPS%20PDK.html

NAND tutorial: https://mole99.uber.space/2024/NAND_tutorial/Design%20of%20a%20NAND%20gate%20using%20the%20ICPS%20PDK.html

1 year ago

24 minutes 25 seconds

Zero to ASIC Course

An interview with Ed Conway - Silicon Supply Chains

Follow Ed here: https://twitter.com/EdConwaySky

Buy his book: https://www.penguinrandomhouse.com/bo...

1 year ago

34 minutes 45 seconds

Zero to ASIC Course

September open source silicon news update - Tiny Tapeout, Conferences, Silicon bringup & more!

00:00 Intro 00:10 TT boards 00:51 TT04 closes on Friday 8th 01:09 ORConf https://orconf.org/ 01:21 Wuthering Bytes 01:53 FSiC videos released https://peertube.f-si.org/video-chann... 02:04 Hackaday Supercon 2023 02:19 YUG2 https://www.linkedin.com/posts/yosysh... 02:36 Silicon news - MPW3 and 2206 03:37 IHP workshop videos • Introduction FMD-QNC project status a... 04:04 IHP cleanroom video footage

2 years ago

4 minutes 33 seconds

Zero to ASIC Course

Interviews from the Free Silicon Conference, Paris, 2023

Interviews with:

Luca Alloatti

Thomas Benz

Jørgen Kragh Jakobsen

Thomas Parry

Rene Scholz

Dan Fritchman

Harald Pretl

2 years ago

21 minutes 36 seconds

Zero to ASIC Course

The MOnSter 6502 - how Eric Schlaepfer built a 6502 processor out of discrete transistors

Website: https://monster6502.com/ & visual 6502 http://www.visual6502.org/JSSim/index.html

Eric's socials: https://twitter.com/TubeTimeUS & https://mastodon.social/@tubetime

Other interviews: https://theamphour.com/609-open-circuits-with-eric-schlaepfer-and-windell-oskay/ & https://unnamedre.com/episode/58

2 years ago

50 minutes 34 seconds

Zero to ASIC Course

First chip designed with ChatGPT? An interview with Dr. Hammond Pearce & Jason Blocklove

https://arxiv.org/abs/2305.13243

00:00 Intro 01:21 Hardware security 02:54 How long have they been using AI to generate Verilog 05:26 Methodology 17:40 Humans in the loop 21:21 Some designs already taped out on TinyTapeout 3 26:49 How to contact

2 years ago

27 minutes 33 seconds

Zero to ASIC Course

Analog ASIC design with digital standard cells!

For TinyTapeout 3, Harald Pretl made an analog temperature sensor out of digital standard cells. In this interview he explains how he did it.

2 years ago

439 hours 7 minutes

Zero to ASIC Course

Jeremy Birch on Tiny Tapeout's static timing analysis

Jeremy Birch implemented a custom STA timing setup for Tiny Tapeout 3. In this interview we discuss his background, what we needed the check and the results.

2 years ago

672 hours 48 minutes

Zero to ASIC Course

using X-rays to make 3D images of chips with Tomas Aidukas

2 years ago

26 minutes 51 seconds

Zero to ASIC Course

Jorge Marín - DC / DC converter design and the IEEE chipathon

2 years ago

36 minutes 4 seconds

Zero to ASIC Course

A look back at 2022 and what I'm looking forward to in 2023

2 years ago

15 minutes 41 seconds

Zero to ASIC Course

September news update: MPW7 & 2, GDS renders, new videos & more!

MPW7: https://zerotoasiccourse.com/post/mpw7_submitted/ MPW2: https://groups.google.com/g/skywater-pdk-announce/c/HelusBBUZ20 Efabless Job: https://www.linkedin.com/jobs/view/3293645910/?refId=BA5W4wSSRYOP%2FlHyVfboBw%3D%3D Correo Libre: https://www.fossi-foundation.org/2022/09/13/ecl54 Interactive GDS viewer: https://mattvenn.github.io/wokwi-verilog-gds-test/viewer/tinytapeout.html Olof's blog: https://www.linkedin.com/posts/olofkindgren_its-time-to-to-thank-uvm-and-say-goodbye-activity-6981904420531777536-iJr4?utm_source=share&utm_medium=member_desktop

3 years ago

4 minutes 30 seconds

Zero to ASIC Course

July news & Free Silicon Conference 2022 (FSiC22)

https://wiki.f-si.org/index.php/FSiC2022 00:00 Intro 01:04 Charles Papon 05:18 Tristan Gingold 09:10 Staf Verhaegen 11:30 Naohiko Shimizu 16:38 Tim Edwards 20:46 Harald Pretl 21:40 Mirjana Videnovic-Misic

3 years ago

26 minutes 29 seconds

Zero to ASIC Course

Crafting open source standard cell libraries with James Stine

00:00 Intro 03:05 Teo's work on optimising adders 04:35 Proppy's work with Jupyter notebooks 05:32 Open source is the key to innovation 07:51 GF180 08:10 When teaching the design of standard cell libraries, what do students struggle most with? 10:15 What does he think engineers least understand, but should, about standard cells? 12:14 What is your tool flow? 16:00 How many cells do you need in a library? 19:24 Why do we need another cell library for GF180? 20:40 How far are we in terms of opensource tools from commercial tools? 22:20 Liberate 25:20 Does he think automated layout of standard cells will be competitive with hand layout in nanometer processes? 29:21 Are there any circuit families from the past that deserve new attention with Moore's Law slowing down? 33:10 Any theories on why nVidia would make a 7.5T standard cell library? Contact James here: james.stine@okstate.edu or on twitter: https://twitter.com/JamesStineJr

3 years ago

35 minutes 28 seconds

Zero to ASIC Course

May news update - MPW6, fast adders, Google's new portal, Free silicon conference, FIB edit

Teo's adders: https://github.com/mattvenn/instrumented_adder MPW6 walkthrough: https://youtu.be/MNuoYz_MM-c https://developers.google.com/silicon Free silicon conference: https://wiki.f-si.org/index.php/FSiC2022 Newsletter: https://www.zerotoasiccourse.com/newsletter/

3 years ago

4 minutes 16 seconds

Zero to ASIC Course

April news update - sky130 on Google colab, optimising adders, $100 tapeout, events and MPW2 wafers

00:00 intro 00:13 moving pictures 00:29 Proppy put sky130 into google colab notebooks: https://colab.research.google.com/gist/proppy/964fa4b9277c3baf9e731872bbad93e4/zerotoasic_project1_1.ipynb#scrollTo=TGgki8I-wPWa 01:12 Teo's work on optimising adders https://blog.yosyshq.com/p/optimising-adders/ 01:53 MPW6 reminder 02:20 Level up your RTL call https://twitter.com/matthewvenn/status/1514927352010186754 02:46 $100 tapeout 04:26 Chips Alliance event https://chipsspring2022.sched.com/ 04:42 WOSET https://twitter.com/mguthaus/status/1521906129126666243 04:57 ChipFlow's first video: https://www.youtube.com/watch?v=rVsOZE80c-k&t=1s 05:28 Ex-ex-ex-clusive MPW2 news 05:45 Maximo's great photo of MPW1 dies: https://twitter.com/maxiborga/status/1522372084671913985

3 years ago

6 minutes 19 seconds

Zero to ASIC Course

Interview with Dinesh A - Riscduino

00:00 Intro

00:45 about Dinesh

02:39 Aim of Riscduino

04:50 Aim to be pin compatible and with support of compiler and libraries

06:10 Join the project - Dinesh is looking for help with analog, verification & embedded

07:30 State of the Analog IP

08:30 Tell us about your applications to MPW2, 3, 4 & 5