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Five Minute VHDL Podcast
Francesco Richichi
33 episodes
8 months ago
Let's talk about hardware design using VHDL
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Technology
Education
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All content for Five Minute VHDL Podcast is the property of Francesco Richichi and is served directly from their servers with no modification, redirects, or rehosting. The podcast is not affiliated with or endorsed by Podjoint in any way.
Let's talk about hardware design using VHDL
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Technology
Education
Episodes (20/33)
Five Minute VHDL Podcast
Q&A#10 RAM Parallelism
How I can parallelize a RAM in FPGA

https://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/


Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses
Show more...
6 years ago
3 minutes

Five Minute VHDL Podcast
ep#22-Multiplier optimization
Learn how to optimize a multiplier in particular cases:

For a technical analysis go to the post:

https://surf-vhdl.link/OptimizationVhdl12b25


Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses
Show more...
6 years ago
5 minutes

Five Minute VHDL Podcast
Ep#21-Serial-to-Parallel Parallel-to-Serial converter
Link to the post:
https://surf-vhdl.link/99990


Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
7 minutes

Five Minute VHDL Podcast
Q&A#09-I need a clock!
In this podcast we will understand how to connect a clock signal to our FPGA


Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses
Show more...
6 years ago
9 minutes

Five Minute VHDL Podcast
Q&A#08- What is the dithering
What is dithering?
Where we can use this technique?

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
4 minutes

Five Minute VHDL Podcast
ep#20-VHDL Generic
VHDL Generic


Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
5 minutes

Five Minute VHDL Podcast
Ep#19-Iterative statement
Even if the VHDL is not a software language, we can find a tyoica SW statement, the iterative statement. Let’s see how to use this

https://t.me/SurfVhdl/92

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
4 minutes

Five Minute VHDL Podcast
Ep#18-the conditional assignment in VHDL
Let’s understand how to implement a conditional statement in VHDL
image for the episode

http://t.me/SurfVhdl/86


Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
7 minutes

Five Minute VHDL Podcast
ep#17-wait
Wait Statements in VHDL
Reference to pictures:

https://t.me/SurfVhdl/82


Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
5 minutes

Five Minute VHDL Podcast
Q&A#07- What is the first thing that a recruiter does?
Q&A#07- What is the first thing that a recruiter does?
When a recruiter needs to hire you as VHDL expert, what do you think he or she will do to understand if you are good for him or her?
What can you do in order to result a VHDL user?
Let’s see in this podcast.

Here you can find the feedback of my VHDL student

https://surf-vhdl.link/vhdl-student

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses
Show more...
6 years ago
4 minutes

Five Minute VHDL Podcast
Ep#16-VHDL process
And now is time to introduce formally a Process
link to the images

https://t.me/SurfVhdl/78

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
7 minutes

Five Minute VHDL Podcast
Q&A#06- How can I generate a new clock from a reference clock?
I receiver a question from Sandip. He got my reference, from my post on DDS.

The question is:
“I want to generate Square of 999kHz, 1000kHz and 1001kHzin VHDL Language and that would be implemented on a Zynq ZC702 evaluation board.
Is it possible by using the DDS.? Can you provide your expertise and comment on it.”

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
10 minutes

Five Minute VHDL Podcast
Ep#15-VHDL Packages
VHDL Packages

http://t.me/SurfVhdl/74

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
3 minutes

Five Minute VHDL Podcast
Ep#14-VHDL object
After signal introduction, let's view what are the remaining VHDL objects

Images
https://t.me/SurfVhdl/72

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
6 minutes

Five Minute VHDL Podcast
Q&A#05- Does the USB transfer work as UART?
I received a question from Haitham. He have to connect a computer to an FPGA using USB connection in order to transfer data from FPGA to the PC.
Haitham is following my VHDL course “Start Learning VHDL Using FPGA”. In this course the last LAB implement communication between PC and FPGA using UART channel.
After starting the course, Haitham asked me: “Does the USB transfer work as UART”?
Let’s see the answer. Here the link to the picture on the telegram channel

https://t.me/SurfVhdl/68

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
9 minutes

Five Minute VHDL Podcast
QA#04-What is the VHDL design flow
In this Q&A episode I want to answer to the question on what is the VHLD design flow
To better follow the episode, see the picture on the telegram channel

https://t.me/SurfVhdl/65

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
7 minutes

Five Minute VHDL Podcast
Ep#13-a way to remember-the flip-flop
Introducing Flip-Flop in VHDL

Link to the picture in the telegram channel

https://t.me/SurfVhdl/61

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
5 minutes

Five Minute VHDL Podcast
QA#3-plzz send the test bench
This is the question many of you ask me very often
I wish to give you some hint and a test bench template I use in my VHDL designs

Here the link to the test bench template: https://t.me/SurfVhdl/58

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
3 minutes

Five Minute VHDL Podcast
Ep#12-VHDL Simulation
A brief overview to setup a ModelSim simulation environment
Link to the episode#12 picture
t.me/SurfVhdl/53

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
5 minutes

Five Minute VHDL Podcast
Ep#11-what is a signal
Introduce signal in VHDL, what is a signal and how to use it.

Image relative to this episode


Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com
Show more...
6 years ago
3 minutes

Five Minute VHDL Podcast
Let's talk about hardware design using VHDL