This is the question many of you ask me very often
I wish to give you some hint and a test bench template I use in my VHDL designs
Here the link to the test bench template:
https://t.me/SurfVhdl/58Website
https://surf-vhdl.comTelegram channel
https://t.me/SurfVhdlYou can contact me
mail:
podcast@surf-vhdl.comTelegram:
https://t.me/francesco_surfvhdlTeachable courses
https://surf-vhdl.link/coursesMusic by Francis Preve -
https://www.francispreve.com