We discuss a novel approach called Tailors that applies principles of speculation to tiling sparse tensors. By intelligently "overbooking" buffer capacities, Tailors is able to maximize reuse of on-chip memory for sparse workloads. We'll also explore Swiftiles, a statistical technique that estimates optimal tile sizes with minimal cost. Tune in to learn how Tailors delivers up to 52x speedups through truly fearless use of hardware resources.
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