As the semiconductor industry struggles with the limits of Moore’s Law, traditional monolithic scaling is no longer enough to meet performance, power, area and cost demands in technology, design, analysis, and manufacturing.
3D IC by Siemens is your go-to podcast for exploring the cutting-edge world of 3D IC packaging—a revolutionary approach reshaping semiconductor design, system integration, and heterogeneous computing.
Join industry leaders, engineers, and innovators as we break down advanced IC packaging solutions like 2.5D/3D IC, FCBGA, FOWLP, and more. Discover how chiplets, multi-die integration, and high-bandwidth memory (HBM) are driving higher performance, lower power consumption, and scalable architectures.
In each episode, we dive deep into the challenges and opportunities of IC design and manufacturing, including:
Roadmap for advanced packaging and heterogeneous integration in semiconductor scaling
Mainstream adoption of 3D IC—key challenges and breakthroughs
Optimizing micro-architecture and integration platforms for performance and efficiency
Strategic planning of chiplets and interposers for hierarchical device integration
Leveraging early predictive multi-physics analysis to enhance design accuracy
Automating design and routing for RDL-based fan-out wafer-level packaging (FOWLP)
Exploring glass substrates for superior electrical and thermal performance
Developing test-vehicles and daisy chain designs for architectural validation
Ensuring reliability and manufacturability in 3D IC heterogeneous integration
Mastering Signal Integrity (SI) and Power Integrity (PI) Analysis for high-speed systems
Managing thermal challenges in stacked die architectures
Subscribe now and stay ahead in the world of 3D IC.
Learn more: Siemens 3D IC Packaging Solutions
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As the semiconductor industry struggles with the limits of Moore’s Law, traditional monolithic scaling is no longer enough to meet performance, power, area and cost demands in technology, design, analysis, and manufacturing.
3D IC by Siemens is your go-to podcast for exploring the cutting-edge world of 3D IC packaging—a revolutionary approach reshaping semiconductor design, system integration, and heterogeneous computing.
Join industry leaders, engineers, and innovators as we break down advanced IC packaging solutions like 2.5D/3D IC, FCBGA, FOWLP, and more. Discover how chiplets, multi-die integration, and high-bandwidth memory (HBM) are driving higher performance, lower power consumption, and scalable architectures.
In each episode, we dive deep into the challenges and opportunities of IC design and manufacturing, including:
Roadmap for advanced packaging and heterogeneous integration in semiconductor scaling
Mainstream adoption of 3D IC—key challenges and breakthroughs
Optimizing micro-architecture and integration platforms for performance and efficiency
Strategic planning of chiplets and interposers for hierarchical device integration
Leveraging early predictive multi-physics analysis to enhance design accuracy
Automating design and routing for RDL-based fan-out wafer-level packaging (FOWLP)
Exploring glass substrates for superior electrical and thermal performance
Developing test-vehicles and daisy chain designs for architectural validation
Ensuring reliability and manufacturability in 3D IC heterogeneous integration
Mastering Signal Integrity (SI) and Power Integrity (PI) Analysis for high-speed systems
Managing thermal challenges in stacked die architectures
Subscribe now and stay ahead in the world of 3D IC.
Learn more: Siemens 3D IC Packaging Solutions
One of the best ways to speed-up product development is to integrate test as early as possible in the design cycle. This shift-left strategy becomes even more critical when advanced IC designs evolve from a single die per package to complex systems with multiple dies integrated into a package. These 2.5D and 3D multi-die design strategies pose some interesting challenges and opportunities for test.
Today, David Lyell interviews Joe Reynick, the Tessent Product Engineering Manager for Siemens EDA. He’ll help us to understand the complexity of development tests for 3D and 2.5D packages.
In this episode, you’ll learn about the challenges of performing comprehensive tests on 3D and 2.5D designs. You’ll also hear about the factors that you need to consider while planning for 3D DFT and IP tests. Additionally, you’ll hear about how 2.5D tests and 3D tests can complement each other.
What You Will Learn In This Episode:
The things you need to be aware of when doing 2.5D and 3D tests (03:34)
The DFT and IP test methods that the DFT and IP test team should implement (09:36)
The die and package level planning interactions needed for 3D DFT and IP test (11:22)
Factors to consider while doing 3D tests (14:20)
What is involved in multi-die IP core test (16:00)
Connect with Joe Reynick:
LinkedIn
Connect with David Lyell:
LinkedIn
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3D IC
As the semiconductor industry struggles with the limits of Moore’s Law, traditional monolithic scaling is no longer enough to meet performance, power, area and cost demands in technology, design, analysis, and manufacturing.
3D IC by Siemens is your go-to podcast for exploring the cutting-edge world of 3D IC packaging—a revolutionary approach reshaping semiconductor design, system integration, and heterogeneous computing.
Join industry leaders, engineers, and innovators as we break down advanced IC packaging solutions like 2.5D/3D IC, FCBGA, FOWLP, and more. Discover how chiplets, multi-die integration, and high-bandwidth memory (HBM) are driving higher performance, lower power consumption, and scalable architectures.
In each episode, we dive deep into the challenges and opportunities of IC design and manufacturing, including:
Roadmap for advanced packaging and heterogeneous integration in semiconductor scaling
Mainstream adoption of 3D IC—key challenges and breakthroughs
Optimizing micro-architecture and integration platforms for performance and efficiency
Strategic planning of chiplets and interposers for hierarchical device integration
Leveraging early predictive multi-physics analysis to enhance design accuracy
Automating design and routing for RDL-based fan-out wafer-level packaging (FOWLP)
Exploring glass substrates for superior electrical and thermal performance
Developing test-vehicles and daisy chain designs for architectural validation
Ensuring reliability and manufacturability in 3D IC heterogeneous integration
Mastering Signal Integrity (SI) and Power Integrity (PI) Analysis for high-speed systems
Managing thermal challenges in stacked die architectures
Subscribe now and stay ahead in the world of 3D IC.
Learn more: Siemens 3D IC Packaging Solutions
